Semiconductor devices such as heterojunction bipolar transistors, lasers, and photodetectors typically are fabricated in Group III-V compound semiconductor bodies. These devices typically have a top major surface that is coated with an insulating layer, such as silicon dioxide, that has an aperture through which a metallic contacting layer makes direct physical and electrical contact with the top surface of the semiconductor body in a region thereof of relatively high electrical conductivity (i.e., either a p.sup.+ - or an n.sup.+ -type semiconductor).
In a paper entitled "Lateral Ga.sub.0.47 In.sub.0.53 As and GaAs p-i-n Photodetectors by Self-Aligned Diffusion," authored by S. Tiwari et al., and published in IEEE Photonics Technology Letters, Vol. 4, No. 4, pp. 396-398, a method of fabricating contacts to the top surface of a Group III-V compound, semiconductor epitaxial layer was taught. The purpose of such contacts is to enable electrical access to the top surface, typically p.sup.+ -type material, of the device that is being fabricated. The contacts p.sup.+ -type regions were fabricated by first forming an insulating layer on the top surface of the epitaxial layer and then forming at least one aperture in this insulating layer, followed by depositing, for example, by sputtering from a zinc-doped tungsten target, a metallic zinc-doped tungsten layer on the top surface of the structure being fabricated. Finally, some zinc is diffused from the zinc-doped tungsten layer into the epitaxial layer by, for example, rapid thermal processing.
Since any physical deposition process, and in particular sputtering, is a spatially non-selective deposition process, it is necessary somehow to pattern the metallic zinc-doped tungsten layer, lest its portions overlying the insulating layer in the device introduce an undesirably high parasitic capacitance (with respect to the epitaxial layer underlying the insulating layer). However, patterning of the metallic layer requires extra processing steps--such as lift-off or spatially selective etching, as by depositing and patterning a resist layer before or after depositing the zinc-doped tungsten metallic layer, respectively--and these extra steps tend to introduce reliability problems. More specifically, a lift-off of the metallic layer undesirably tends to lift off the underlying insulating layer. Moreover, any zinc-doped tungsten remaining, after the selective etching, anywhere on the surface of the insulating layer can undesirably result in a diffusion of zinc from the zinc-doped tungsten layer through the insulating layer to the epitaxial layer, whereby unwanted parasitic conducting paths in the epitaxial layer can be formed. Furthermore, in any case, the zinc that is present in the metallic layer can undesirably out-diffuse from the top surface of this metallic layer and thereby contaminate, and even reduce the electrical conductivity of, an overlying layer of another metal, such as gold, which is typically used for metallizing desired electrically conductive paths for electrical access to the device.
Moreover, sputtering as a process for depositing a layer of metal with a metallic impurity incorporated in it--such as the aforementioned layer of zinc-doped tungsten--has a disadvantage, whether the sputtering is performed with a single metallic target composed of the metal plus the impurity or with two pure targets (one composed of the metal, the other of the impurity). In the former case (single target), the composition of the single target is not stable owing to out-diffusion of the impurity at the elevated temperature of the target during the sputtering (bombardment of target) process, whereby the composition of the deposited layer is difficult to control, especially when processing one semiconductor body after another (as is desirable for sequential processing of many semiconductor devices). In the latter case (two targets), complex control systems are required to maintain the deposition rates of the two metals at the desired ratio, which can be undesirably costly.